TCLUG Archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Mail failure

TO: Chris Kesler                                               DATE: 02-25-99
                                                               TIME: 20:24
SUBJECT: Mail failure

[002] Mail was received that was addressed to unknown addresses.
Mail item was not delivered to:

   From: Chris Kesler []
     To: tclug-list []
   Date: 1999-02-25 20:23
Subject:  Re: [TCLUG:4297] InstallFest swap meet


On Thu, 25 Feb 1999, Chris Schumann wrote:

> On Thu, 25 Feb 1999, Michael Hicks wrote:
> > IIRC, memory speed has to be something on the order of 8ns to qualify as
> > PC100.
> 1 / 100MHz = 10ns cycle time. Usually, the address is already presented to
> the memory at the beginning of the cycle, so data must appear some minimum
> time before the cycle ends, so 8ns sounds about right.
> Chris Schumann <>

I've heard that before, too (in fact I mentioned to someone earlier today
that I thought 8 ns is PC100).  But when says
otherwise, I bow down.  I assume that this is important to all of us, or
soon will be, so here's what I found today:

To ensure a stable 100 MHz operation, 5 ns 2nd level cache chips are
required which still are more expensive than the 6 or 7 ns types.
Therefore some manufacturers use selected 6 ns chips. But be careful: The
system won't have any tolerances in case you plan to overclock it!

There is still quite a bit of confusion regarding what a ?true? PC100
module actually consists of.  Unfortunately, there are quite a few modules
being sold today as PC100, yet do not operate reliably at 100MHz. While
the chip speed rating is used most often to determine the overall
performance of the chip, a number of other timings are very important.
tRCD (RAS to CAS Delay), tRP (RAS precharge time) and CAS Latency all play
a role in determining the fastest bus speed the module will operate on to
still achieve a 4-1-1-1 timing.

PC100 SDRAM on a 100MHz (or faster) system bus will provide a performance
boost for Socket 7 systems of between 10% and 15%, since the L2 cache is
running at system bus speed. Pentium II systems will not see as big a
boost, because the L2 cache is running at 1/2 processor speed anyway, with
the exception of the cacheless Celeron chips of course.


The above are dated July and October of 1998.


To unsubscribe, e-mail:
For additional commands, e-mail:
Try our website: